			IDE/ATA CONTROLLER Reference Design
===============================================================================
 
1. /docs/RD1095.pdf                 										--> Design document
   /docs/rd1095_readme.txt          										--> Read me file (this file)
   
2. /project/xo/verilog/ide_controller.syn        				--> Project file
   /project/xo/verilog/test_bench_top_tff.udo   				--> Functional Simulation script
   /project/xo/verilog/test_bench_top_tf.udo    				--> Timing Simulation script   
   /project/xo/verilog/ide_controller.lpf         			--> preference file   
   
  
3. /Source/Verilog/atahost_top.v               					--> Source file
   /Source/Verilog/atahost_wb_slave.v           				--> Source file
   /Source/Verilog/atahost_controller.v               	--> Source file
   /Source/Verilog/atahost_pio_controller.v             --> Source file
   /Source/Verilog/atahost_pio_actrl.v                 	--> Source file
   /Source/Verilog/atahost_pio_tctrl.v              		--> Source file
   /Source/Verilog/atahost_dma_actrl.v                  --> Source file
   /Source/Verilog/atahost_dma_tctrl.v                  --> Source file
   /Source/Verilog/atahost_fifo.v            						--> Source file
   /Source/Verilog/atahost_lfsr.v                       --> Parameter file
   /Source/Verilog/atahost_reg_buf.v                		--> Source file
   /Source/Verilog/ro_cnt.v               							--> Source file
   /Source/Verilog/ud_cnt.v                     				--> Source file


4. /Testbench/verilog/test_bench_top.v          				--> Testbench for simulation
   /Testbench/verilog/ata_device.v                    	--> ATA card behavioral model
   /Testbench/verilog/tests.v             							--> test_vector
   /Testbench/verilog/wb_mast_model.v                 	--> WISHBOEN master model
   /Testbench/verilog/wb_model_defines.v          			--> Wishbone master parameter define
      

How to open the ispLEVER project:
1. Unzip the RD1095_revyy.y.zip file using the existing folder names, where yy.y is the current
   version of the zip file 
2. Open the ispLEVER Project Navigator.
3. In the File menu, click on Open Project, then browse to the directory where the reference 
design was unzipped to.  Select the RD1095\Project\<Device>\<HDL-Language>\ide_controller.syn file and click open.

How to run simulation:
1.  In the Project Navigator, highlight the ..\..\..\testbench\verilog\test_bench_top.v file on the
left-side panel, user will see 3 simulation options on the right panel.
2.  For functional simulation, double click on Verilog Functional Simulation with
Aldec Active-HDL. Aldec simulator will be brought up, click yes to overwrite the
existing file.
3.  Functional simulation will run until completed and the simulation should end 
without error.
4.  For timing simulation, double click on Verilog Post-Route Timing Simulation
with Aldec Active-HDL. Similar message will be shown in the console panel of the
Aldec Active-HDL simulator.

How to run Place and Route, JEDEC generation, and Timing Analysis:
1. Highlight the device on the left-side panel of the Project Navigator. On the
right-side panel, double click on Place and Route Design. This will bring the
design through synthesis, mapping, and place and route.
2. Highlight the device on the left-side panel of the Project Navigator. On the
right-side panel, double click on Generate Data File (JEDEC). This will generate
the jedec file for the design.
3. Once Place and Route is done, user can double click on Place and Route Trace
Report on the right-side panel to get the timing analysis result.
