DEC Alpha, ARM, MIPS, PowerPC, SPARC, VAX, PDP-8 и другие устройства
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bbr
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Сообщение
bbr » 23.01.2022,17:55
SUN Ultra Server 1, в добром здравии, дремелинг IDPROM прошёл успешно.
Внезапно при POST начал жаловаться на память (при первых включениях не жаловался):
0> Writing SIMM Pair 2 base address 00000000.20000000
0> Data Access Error
0> 00000000.00100000 AFSR(Status)
00000000.20005300 AFAR(Address)
0> Access Error Registered
0> 00000000.00100000 AFSR(Status)
00000000.20005300 AFAR(Address)
0>Memory address 00000000.20005300 in SIMM Pair 2, SIMM 0
0>SDB for this address is: U0301
0>SIMM U0603 or System Board
0> (CE) Correctable ECC Error
0> SDBH[143:72] Syndrome is 52
0>
CE Error on Data bit 93
0>Data Bits[92:95] in BMX U0902
Полный лог консоли:
► Показать
0>@(#) Sun Ultra Enterprise 1 UPA/SBus POST 3.11.4 5/27/1997 02:26 PM
0> UltraSparc 1 Version 2.2
0>RESET SC Control=00000000
0> SC id is 33403000 (UPA Number 3)
0>NVRAM Walking 0 and 1 Test
0>Probe, Test and Initialize Ecache
0> ECache RAM Size = 00080000
0> ECache TAG Size = 00002000
0>Testing 512 Kbytes Ecache RAM
0>Probing DSIMM's ...
0>SIMM Pair Base Addr Low Size Hi Size Pair Status
0> 0 00000000.00000000 32Mb 32Mb 00
0> 1 00000000.10000000 32Mb 32Mb 00
0> 2 00000000.20000000 64Mb 64Mb 00
0> 3 00000000.30000000 128Mb 128Mb 00
0> SIMM Present Field 00000f00
0> ***** Found total 512 Mb of usable Main Memory *****
0>Running at Frequency 167 MHZ
0>Setting MC_Control1 to 0000026a
0>Setting MC_Control0 to 80000f14 (4,0)
0>Quick Memory Test
0>UPA Cacheable Data and Check bit Bits
0>Stack Memory Test (memory_offset=00000000.00000000)
0>SelfTest Initializing
0>EPROM Path Test
0> PROM Datapath Test
0>PROM Datapath Test PASSED
0>FPU Register Test
0> FSR Read/Write Test
0>FSR Read/Write Test PASSED
0>NVRAM Test
0>MMU Enable Test
0> DMMU Registers Access Test
0>DMMU Registers Access Test PASSED
0> DMMU TLB DATA RAM Access Test
0>DMMU TLB DATA RAM Access Test PASSED
0> DMMU TLB TAGS Access Test
0>DMMU TLB TAGS Access Test PASSED
0> IMMU Registers Access Test
0>IMMU Registers Access Test PASSED
0> IMMU TLB DATA RAM Access Test
0>IMMU TLB DATA RAM Access Test PASSED
0> IMMU TLB TAGS Access Test
0>IMMU TLB TAGS Access Test PASSED
0> DMMU Init
0>DMMU Init Test PASSED
0> IMMU Init
0>IMMU Init Test PASSED
0> I/D MMU TLB Load and Initialize
0>I/D MMU TLB Load and Initialize Test PASSED
0>Serial Ports Test
0> Serial Port Register Test
0>Serial Port Register Test PASSED
0> Serial Ports Test
0>Serial Ports Test PASSED
0>Ecache Test
0>Basic CPU Test
0> Instruction Cache Tag RAM Test
0>Instruction Cache Tag RAM Test PASSED
0> Instruction Cache Instruction RAM Test
0>Instruction Cache Instruction RAM Test PASSED
0> Instruction Cache Next Field RAM Test
0>Instruction Cache Next Field RAM Test PASSED
0> Instruction Cache Pre-decode RAM Test
0>Instruction Cache Pre-decode RAM Test PASSED
0> Data Cache RAM Test
0>Data Cache RAM Test PASSED
0> Data Cache Tags Test
0>Data Cache Tags Test PASSED
0>Memory Test
0> Memory Control Register Init
0>Running at Frequency 167 MHZ
0>Setting MC_Control1 to 0000026a
0>Setting MC_Control0 to 80000f14 (4,0)
0>Memory Control Register Init Test PASSED
0> Memory Clear Test
0>Memory Clear Test PASSED
0> Memory RAM (blk) Test
0>Memory RAM (blk) Test PASSED
0> Memory Address Line Test
0> Writing SIMM Pair 0 base address 00000000.00020000
0> Writing SIMM Pair 1 base address 00000000.10000000
0> Writing SIMM Pair 2 base address 00000000.20000000
0> Data Access Error
0> 00000000.00100000 AFSR(Status)
00000000.20005300 AFAR(Address)
0> Access Error Registered
0> 00000000.00100000 AFSR(Status)
00000000.20005300 AFAR(Address)
0>Memory address 00000000.20005300 in SIMM Pair 2, SIMM 0
0>SDB for this address is: U0301
0>SIMM U0603 or System Board
0> (CE) Correctable ECC Error
0> SDBH[143:72] Syndrome is 52
0>
CE Error on Data bit 93
0>Data Bits[92:95] in BMX U0902
Power On Selftest Completed
Status = 0000.0000.0000.0001 ffff.ffff.f007.4268 0e66.0010.0180.1d00
Software Power ON
@(#) Sun Ultra 1 UPA/SBus 3.11 Version 1 created 1997/12/03 15:44
Clearing E$ Tags Done
Clearing I/D TLBs Done
Probing Memory Done
MEM BASE = 0000.0000.3000.0000
MEM SIZE = 0000.0000.1000.0000
MMUs ON
Copy Done
PC = 0000.01ff.f000.1c7c
PC = 0000.0000.0000.1cc0
Decompressing into Memory Done
Size = 0000.0000.0006.5ed0
ttya initialized
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Probing Memory Bank #0 32 + 32 : 64 Megabytes
Probing Memory Bank #1 32 + 32 : 64 Megabytes
Probing Memory Bank #2 64 + 64 : 128 Megabytes
Probing Memory Bank #3 128 + 128 : 256 Megabytes
Probing UPA Slot at 1e,0 SUNW,ffb
Probing /sbus@1f,0 at e,0 SUNW,fas sd st SUNW,hme SUNW,bpp
Probing /sbus@1f,0 at 0,0 Nothing there
Probing /sbus@1f,0 at 1,0 SUNW,hme SUNW,fas sd st
Стоит ли заморачиваться или "ну и фиг с ней - Correctable же"?
Если заморачиваться, то видимо надо и планки и мать в Трилон-Б мыть, окислы снимать. Хотя визуально сервак весьма чистый и при первых включениях этой ошибки не вылезало...
bbr