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Digital AlphaPC 164LX 599 MHz Console V5.3-3, Sep 24 1998 14:02:11
...
>>>show memory

128 MBytes of system memory

Bank #       Size     Base Addr
------    ----------  ---------
  0         128 MB    000000000

Total Bad Pages = 0
Total Good Memory = 128 MBytes

Bcache Size = 2 MB
>>>

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 * (conf-6) bit6:  Mini-Debugger (0=enabled 1= disabled)        [23]
 * (conf-5) bit5:  BC_Speed<0>                                  [19]
 * (conf-4) bit4:  BC_Speed<1>                                  [20]
 * (conf-3) bit3:  PASSWORD Bypass
 *
 *              BC_Speed<1:0>   Bcache
 *              ------------    -------
 *                 00           Reserved
 *                 01           Reserved
 *                 10           Reserved
 *                 11           9ns (default)
 *

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//++
// ===========================================================================
// = srom_size_memory - size the main memory for volume                 =
// ===========================================================================
//
// OVERVIEW:
//
//        This function will size the main memory on an bank per bank basis
//
// FORM OF CALL:
//
//       bsr r26,srom_size_memory
//
// ARGUMENTS:
//
//      none
//      
// RETURNS:
//
//     r10 - size mask with total size of configurable memory
//     r11 - upper LW is speed of slowest DIMM on memory bus
//           lower LW is 1 if all DIMMs have ECC bits, else 0
//
// FUNCTIONAL DESCRIPTION:
//
//      This code uses the following definitions and assumptions:
//
//      1. A PC164LX / EV56+PYXIS based board will contain from 1 to
//         two populated banks of SDRAM DIMMS.  Each bank will
//         consist of two DIMMS to create the 128 bit wide memory
//         bus.
//      2. Each DIMM is JEDEC JC-42.5-95.164 compliant or better.
//         Thus each DIMM will have a JEDEC compliant IIC ROM
//         containing full DIMM specification data.
//      3. DIMMS in each bank must be IDENTICAL in almost every
//         way.  In addition all DIMMS will must meet a minimum
//         set of timing specifications determined by reading the
//         IIC ROM on each DIMM.  SDRAM DIMMS come in many more
//         speed variants than older 72 pin SIMMs, and many are too
//         slow for EV56 + PYXIS.
//      4. Single, Dual, and Quad bank DIMMS are supported in sizes
//         from 16MB up to 256MB using either 16Mbit or 64Mbit SDRAMS.
//      5. PYXIS supports eight total banks, though PC164LX only uses
//         two.
//
//
//      This function will size the amount of memory in the system by
//      reading the IIC ROM for each DIMM.  Banks containing mismatched
//      DIMMS will cause an error beep code and prevent normal machine
//      operation.
//
//      A data structure of the following format is built as a 
//      result of the memory sizing.  It represents the DIMM size
//      in a given bank.  PC164LX has two banks, and PYXIS supports eight.
//
//      PC164LX size_mask (DIMMs):
//      =========================
//       63          56 55            48 
//      +--------------+----------------+
//      | 8MB          | 16MB           |
//      +--------------+----------------+
//
//       47          40 39            32
//      +--------------+----------------+
//      | 32MB         | 64MB           |
//      +--------------+----------------+
//
//       31          24 23            16
//      +--------------+----------------+
//      | 128MB        | 256MB          |
//      +--------------+----------------+
//
//       15           8 7              0
//      +--------------+----------------+
//      | 512MB        | 1GB (!!)       |
//      +--------------+----------------+
//
//       Each bit within the size fields corresponds to a memory dimm size.
//      This means that for a particular bank only one bit can be set in a 
//      particular field:
//      
//      I.E.
//
//      if bank 1 is configured as a set of 128MB DIMMs then
//      bit 1  = 0   (it IS NOT a 1GB DIMM)
//      bit 9  = 1   (it IS     a 512MB DIMM)
//      bit 17 = 0   (it IS NOT a 256MB DIMM)
//
...

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// BCR0-BCR7 - Bank Config Reg
//              [0]   bank_enable if set
//              [4:1] Bank Size
//                 1000   2GB  ** PYXIS is capable of these configs
//                 0000   1GB  ** but is not tested or documented.
//                 0001 512MB
//                 0010 256MB
//                 0011 128MB
//                 0100  64MB
//                 0101  32MB
//                 0110  16MB
//                 0111   8MB 
//              [5]   Sub Bank Enable
//              [6]   ROW sel 0=12, 1=14
//              [7]   4BANK

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// The following tests are made against each DIMM before it is
// sized.  These checks insure electrical compatibility with
// PC164LX & PYXIS, considering the huge range on many of the
// DIMM characteristics.  
// 
// Any DIMM which does not pass these initial checks will cause 
// a fatal error with beep codes, as the whole memory subsystem 
// will become unusable.

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//  6     64|72  ** 72 only for PC164LX I

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// : //check for DIMM pair mismatch on odd slot numbers
// : if ((dimm_slot&1)==1)
// : : if (match_col==col) && (match_row==row)
// : : : //everything checks for DIMM so populate bitmap
// : : : //each dimm is 8 bytes wide
// : : : dimm_size=1<<(col+row+3+sub_bank+SDRAM_4bank)
// : : : mputs("DIMM")   mputs(" siz")  mputs("e:0x")
// : : : putl dimm_size  mputs("MB  ")
// : : : //2^27 is largest DIMM supported, set bit corresponding to 
// : : : //size of dimm and position of slot. 2^27*8=1GB
// : : : size_mask |= 1<<[((27-row-col)<<3)+(dimm_slot>>1)]
// : : else
// : : : mputs("Error! DIMM Size mismatch slots #")
// : : : putl(dimm_slot-1)  mputs(" and #") putl(dimm_slot)
// : : : feature_mask |= 1<<((slot>>1)+56) //put a mismatch flag in
// : : : maybe beep(1,1,3)
// : : end
// : else 
// : : match_row=row
// : : match_col=col
// : end